郭明錤｜Ming-Chi Kuo@mingchikuo · X郭明錤分析，台积电CoPoS预计2028下半年量产，面向9.5倍光罩尺寸以上超大封装，NVIDIA Feynman AI芯片或率先采用。玻璃用于两个位置：310×310mm临时载板，以及250×250mm（试产）/510×515mm（量产）玻璃面板加工成玻璃核心基板。该基板为三层结构——玻璃芯两侧叠加ABF增层，TGV成孔与铜填充等挑战集中于此处。澄清常见误解：玻璃非中介层，互连由RDL、TGV/Cu及ABF共同承担；玻璃与ABF共存而非替代；芯片贴装在ABF增层表面。CoPoS有望延续台积电先进封装领先优势至2032年左右。
Key takeaways on TSMC's next-generation advanced packaging， CoPoS （publicly available technical details omitted）：
1. CoPoS is currently expected to enter mass production in 2H28. It is designed to improve the economics of ultra-large packages above the 9.5x reticle-size class， with NVIDIA's Feynman AI chip a potential first adopter.
2. According to industry checks， glass is used in two distinct places （dimensions in mm）： → 310 x 310 temporary glass carriers → 250 x 250 （pilot） / 510 x 515 （mass production） glass panels， processed and later cut into individual glass core substrates
3. The glass core substrate is essentially a three-layer structure： a glass core sandwiched between ABF （ABF-GCP） build-up layers on both sides. The widely discussed glass processing challenges， such as TGV formation and copper filling / metallization， are tied to this part of the stack.
4. Common misconceptions about CoPoS： → ❌ Misconception 1： CoPoS uses a glass interposer. ⭕️ Correction： The glass is not an interposer. The interconnect role is instead handled by the chip-side RDL， plus the TGV/Cu interconnects and ABF build-up layers in the glass-core substrate stack. → ❌ Misconception 2： Glass replaces ABF. ⭕️ Correction： As the substrate architecture above shows， glass and ABF coexist. → ❌ Misconception 3： Chips sit directly on glass. ⭕️ Correction： Chips are attached to the ABF build-up surface of the glass core substrate.
5. CoPoS should extend and reinforce TSMC's leadership in advanced packaging， potentially giving that advantage visibility through around 2032.